Answers to your data-retention specs and testing questions

Also, troubleshooting flowcharts for parallel NOR and dongle detection details

 

Q: My project will be using the Cypress S25FS128S flash device and I have some questions about your data-retention specs as they relate to our project. Our application will program the flash device only one time, and over the course of 20 years it will be exposed to a temperature range of -46°C to +74°C. My questions are:

 

  • Will the S25FS128S flash device meet our data-retention requirements?
  • What are your data-retention testing methods?
  • How does program cycling affect data retention?

A: The Cypress S25FS128S Serial NOR flash device will meet the data-retention requirements for 20 years, as long as the temperatures during operation do not exceed the datasheet specification. The datasheet temperature-range specs are:

 

  • Industrial applications: 0°C to +85°C
  • Automotive applications: -40°C to +105°C

There should be no concern about the data retention under these conditions because this is a low-cycle application. Operating outside of the specified temperature range, however, could affect the data retention of the device.

 

Our data-retention testing methods include performing cycling at 1,000, 10,000, and 100,000 cycles. We then perform data-retention tests on the cycled parts using a 150°C retention bake. The tests are performed in accordance with JESD47/JESD22-A117 and AEC-Q100-005. Feel free to refer to “Practical Guide to Endurance and Data Retention,” which describes the trade-off between cycling and retention.

 

We also perform data-retention calculations based on a specific usage profile, if one is provided. For example, a profile may suggest that the device is exposed to the following range of temperatures for the given percentage of time during the 20-year period:

 

  • -40°C for 5% of the period
  • -25°C for 10% of the period
  • 0°C for 15% of the period
  • 25°C for 50% of the period
  • 55°C for 10% of the period
  • 75°C for 5% of the period
  • 90°C for 5% of the period

In the absence of a usage profile, however, we can only apply an average temperature based on the range. For the specific range mentioned in your question, -46°C and 74°C, the nominal assumption is 14°C. This is well within the operating temperature range of this device.

 

You may also refer to the latest revision of JEDEC Publication 122. Simply put, the fundamental failure mechanism for data retention in flash memory is purely Arrhenius based; that is, higher temperatures accelerate the detrapping of electrons, resulting in eventual charge loss. The specific time distribution—for example, the fact that there may be daily, versus monthly, cycling from hot to cold—has no effect on the core memory cell. There could be some type of package-related issue, but that is why we perform temperature cycling, to look for any kind of degradation. We program a pattern into the flash device during temperature cycling and check the pattern at the end of the test to look for failure.

 

I’d also recommend reviewing the S24FS128S datasheet.

 

 

Q. Do you have any troubleshooting flowcharts available that can help me with my Cypress parallel NOR (PNOR) flash device?

 

A. Yes, in fact, we have what’s called a flash debugging flowchart for PNOR that may be helpful for you to use (see figure 1).

 

 

V2N2 Top Tips review Picture 1

 

Figure 1: Flash memory device debugging flowchart helps guide users through the debugging process; pay attention to the notes listed because they include valuable tips.
 

Before you get started using this, there are a few assumptions that I’d like to mention here. Bear with me, because some of these may seem fairly obvious, but are worth noting and checking.

 

  1. The board signals must be routed to the proper locations.
  2. The board signals need to be able to rise and fall according to the datasheet parameters (no shorts/opens).
  3. Power On Reset (POR) timing must be within the specifications outlined in the respective PNOR datasheet.
  4. The read and write timing must be within the specifications outlined in the datasheet.
  5. The device must be chip-enabled to read and write to it. Chip enable is generated by the CPU when the proper address is selected.

Before trying any software to see if the PNOR flash device works, it is much simpler to use an emulator to exercise basic functions. By using the emulator, you can completely remove the software from the list of possible problems. It also provides a simple way to display memory and to perform reads and writes. If these basic functions work, then the majority of the hardware connections must be fine. The first step would then be to program the processor’s memory controller with the base address, size and timing parameters of the device. When that is done, reads and writes to that address range should chip-select the flash device.

 

Refer to the following notes where specified in the debugging flowchart.

 

Note 1: When erase is suspended, a Program Suspend command could be issued accidentally by the software after the programming is finished. The associated Program Resume will resume the erase.

 

Note 2: Most commands are ignored when issued during a program or erase operation. A common error occurs when initiating a new operation before the current operation is complete, due to an incorrectly-coded polling function. You should look at or use a low level driver (LLD).

 

Note 3: In PLxxxJ, programming or verifying the SecSi sector lock bit, access to the main array may be temporarily blocked.

 

 

Q. I’m having some trouble getting my CY8CKIT-042-BLE dongle to be recognized by my CySmart windows application. Do you have any troubleshooting tips I can follow?

 

A. You’ve come to the right place. Of course I have some suggested steps you can follow to correct the issue. Please follow these in the order listed to help ensure your success.

 

  1. Plug in the CY8CKIT-042-BLE dongle to your PC and open the CySmart application. If the dongle shows up as unsupported, press the reset switch on the dongle. If this does not show the dongle in the supported devices list, follow step 2.
  2. Open Device Manager and make sure the dongle is listed as “KitProg USB-UART (COM)” under “Ports (COM and LPT).” If the dongle is listed under a different name such as “USB Serial Port (COM),” it means the dongle is mapped to the wrong USB serial-port driver. At this point, you should update the driver to manually bind to the KitProg USB-UART driver available in this folder:

C:\Program Files(x86)\Cypress\Programmer\drivers\KitProg

 

If the above step does not resolve the issue, the firmware of the dongle has to be upgraded as shown in steps 3 and 4 below.

  1. Open PSoC Programmer and upgrade the dongle firmware (for the PSoC 5LP) by navigating to the utilities folder and clicking on “Upgrade.” For more details on upgrading the firmware, refer to the document “PSoC® 4 Pioneer Kit (CY8CKIT-042) Factory Restore Instructions for Programmer and Debugger Functionality—KBA87474” online here.
  2. Once the firmware for the PSoC 5LP is upgraded, the PSoC 4 BLE firmware can be upgraded by programming the hex file “BLE Dongle CySmart 1.1.0.17.hex” using the PSoC Programmer. You can find this file online about half-way down the page here. Make sure to choose the programmer settings that are relevant to PSoC 4 BLE.
  3. The above steps should resolve the issue for you. However, if the issue still persists, try plugging the dongle into a different USB port on your computer. You should also reboot your computer after the driver and the firmware upgrade.
  4. Of course, if you have any additional questions or if the issue above is still not resolved, please contact Cypress Technical Support by either creating a case online or calling 800.541.4736 or 408.943.2600 and selecting option 2.

 

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