PMICs with I2C cut power consumption in SoCs

Adding I2C communications functionality to power management IC simplifies design and reduces leakage current.

Takeaways

  • Communications-enabled PMICs reduce leakage current.
  • Optimizing power sequence via software shortens development time.
  • The approach minimizes mounting area.

 

Recent SoCs such as FPGAs have led to the need for core/DDR interfaces/peripheral IC interfaces and multiple power supply systems. The start/interrupt sequences for these have also become more complex. In addition, the increase in leakage current due to evolution of technologies has become serious. For that reason, we have introduced a method for power supply start/interrupt sequence design and reduction of leakage current using a power supply equipped with I2C communications functionality.

 

The current leakage problem

The past few years have seen an increasing number of multi-channel power management ICs (PMIC) equipped with an SPI/I2C communications interface. Spansion has also started to offer PMICs equipped with an I2C interface for the SoC, which is the main engine of systems. Using I2C-enabled PMICs allows designers to simplify power supply start/interrupt sequence design, reduce mounting surface, and drop leakage current. This document introduces the related techniques.

 

The core voltages of recent SoCs have been going one way—downward. In particular, with 20-nm FPGA technology, a low power voltage at 0.9 V is being sought. For DRAMs such as DDRs, the power voltage also has been dropping but at 1.35 V for DDRR3L and 1.5 V for DDR3, these have higher voltage in comparison to core voltages. Meanwhile, many peripheral ICs like flash memory require 3.3 V. For that reason, SoCs such as ASIC/FPGA/ASSP that shoulder large-scale data processing such as video processing require multiple power supply systems for the core/DDR interfaces and  peripheral IC interface. Furthermore, most systems need fine sequence control to prevent current leakage caused by unstable logic output during power start/interrupt or by excess inversion of internal power voltage relationship.

 

Because of the increase in leakage current that has accompanied the evolution of technology, SoC makers are facing problems with heat generation during operation and with increased power consumption in standby mode. As countermeasures, attention is being focused on dynamic voltage scaling (DVS) for changing the voltage according to the operational mode, and on adaptive supply voltage (ASV) for setting optimal power voltage according to process completion (slow/fast).

 

Simplification of power sequence design

To prevent SoC current leakage caused by unstable logic of the output terminal at start/interrupt, designs generally use a core power –> I/O power startup sequence. Furthermore, to prevent leakage due to excess inversion of internal power voltage relationships, in many cases a start/shutoff sequence is also specified for each I/O voltage. Because the requests for power line start/shutoff probe and interval differ for each system, formerly it was necessary to change the hardware at each change of the system.

 

On the other hand, a communications control capable PMIC is able to execute by overwriting the ON/OFF protocol, the output voltage settings, and the settings for the soft start time in the registers within the PMIC (see figure 1).  For that reason, adjustments in sequence can be implemented with only a change in software, not in the hardware (see figure 2).

 

v1n3 pmic fig1

Figure 1: MB39C031 enables designers to change the power start/shutoff pattern by changing only the MCU communications program, without changing the hardware.

 

 

Figure 2: MB39C031 enables the use of register setting to set output voltage, soft start time, ON/OFF for each channel, and selection of PFM/PWM auto-switching mode or PWM mode.

Figure 2: MB39C031 enables the use of register setting to set output voltage, soft start time, ON/OFF for each channel, and selection of PFM/PWM auto-switching mode or PWM mode.

Furthermore, many communications control capable PMICs are multi-channel. This leads to a smaller mounting surface area than for a conventional one-channel product, with a 30% reduction compared to a three-channel product (see figure 3).

 

Figure 3: The MB39C031 PMIC uses a mounting surface of 89-mm2 for two-channel step-down DC/DC converter and a one-channel LDO.

Figure 3: The MB39C031 PMIC uses a mounting surface of 89-mm2 for two-channel step-down DC/DC converter and a one-channel LDO.

 

Reduction of leakage current

Let’s take a closer look at how a PMIC can be used to control leakage current.

 

Dynamic Voltage Scaling (DVS)

In the core power supply of an SoC, higher voltages are required as a result of the voltage drop from parasitic resistance in the substrate and power wiring resistance within the SoC. Because the voltage drop becomes smaller in a state with light load, such as in standby mode, it is possible to lower the power voltage in comparison to a state in which there is constantly a heavy load.

 

With systems that cannot change the PMIC output voltage, excess voltage continues to be applied to the SoC when in standby mode (light load). Power consumption due to leakage is dependent on voltage, so this results in excess consumption of power. Therefore, by using a PMIC that varies the output voltage according to the state of operation, it is possible to set an optimal voltage for the operational mode. In this way, it is possible to minimize the power consumption due to leakage. This is especially effective in systems that have long standby times.

 

Figure 4: DVS Operational Concept Diagram

Figure 4: DVS Operational Concept Diagram

Adaptive Supply Voltage (ASV)

The lag time in the signal line within an SoC is voltage dependent–the higher the power voltage, the shorter the lag time. In addition, the operational frequency of the SoC will be restricted by the lag time of the critical path when process conditions are slow. For that reason, the power voltage under slow conditions is excessive when under fast conditions.

 

By lowering the power voltage for the critical-path lag time under fast conditions to be equal with the time under slow conditions, it is possible to reduce both the operational current and leakage current. ASV is a method gaining attention for its ability to lower the maximum consumption current of an SoC.

 

In application, first decide the output voltage setting register value of the PMIC for each process condition, based on the relationship of the power voltage and the process conditions offered by the SoC manufacturer (see figure 5). This provides the ability to use communications to set the output voltage before operation of the SoC or after start with the TYP voltage.

 

Figure 5: ASV Explanatory Diagram

Figure 5: ASV Explanatory Diagram

We have introduced the approach of using a communications control capable PMIC for simplification of power supply sequence design and for issues faced by advanced SoCs in the form of reduction of power consumption. Although the market is changing with increasing speed, the ability to design the power sequence by changing only the software contributes to the shortening of development time. Moreover, increased SoC functionality and decreased power consumption were formerly targeted by future technical developments but ASV/DVS offer an approach from another perspective.

 

Investigating the linking of SoCs and PMICs from the first stages of development enables gains in low power consumption for systems without the cost increases that accompany the evolution of technology. In conjunction with the seriousness of increasing leakage current, it can be thought that power solutions optimized at the system level will be all the more important going forward.

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