- Bluetooth Smart uses Bluetooth Smart Ready installed base to simplify interoperability.
- System-on-chip (SoC) solutions increase efficiency of wearables design and development.
- SoCs include processors, memory, power management capabilities, Bluetooth radio, etc. to enable a high level of interoperability.
Simplify wearables development using system-on-chip designs
Wearable technology has achieved remarkable user adoption, as the devices help analyze one’s daily routine and allow information exchange in a user-intuitive way, greatly improving our ease and style of living. There is a variety of wearable electronics available in the market, the most prominent being smartwatches, activity monitors and fitness bands. These highly portable products are worn or otherwise attached to the body, and are capable of measuring or capturing information via one or more sensors (see figure 1).
Figure 1: A typical wearable device combines user data with external data, working in tandem with an external device to analyze and present information to the user.
These devices continuously monitor a user’s activities, even when the user is sleeping. They run complex algorithms to extract meaningful information, such as the soundness of the wearer’s sleep, and present the results in a user-intuitive way via a wireless interface. Because these devices provide what may be vital information that could potentially change a person’s activities, they have to be reliable and accurate. They also need to be as efficient as possible to maximize the battery life.
A wearable device typically includes one or more sensors, a processor, storage, connectivity (radio controller), a display and a battery (see figure 2). Apart from delivering high functionality, reliability and power efficiency, wearable devices also need to be small, lightweight, low cost and able to support different communications modes.
Figure 2: Block diagram of a wearable device shows the MCU, sensor, flash memory, battery and power management devices, connectivity subsystem and display.
Communications protocols available on the market include standards like ZigBee, Wi-Fi and classic Bluetooth, as well as proprietary versions developed by silicon vendors. The standard protocols were not designed with low power as one of the key features, so for a long time, most OEMs chose to use proprietary protocols in their low-power products. Usage of these proprietary protocols imposes a lot of interoperability restrictions and reduces the flexibility of designs, however.
To address these limitations and create an interoperable environment, the Bluetooth Special Interest Group (SIG) introduced a new version of Bluetooth known as Bluetooth Smart, designed to be a wireless standard with the lowest possible power usage for short-range communication.
The benefits of Bluetooth Smart
Just like classic Bluetooth, Bluetooth Smart operates in the 2.4 GHz ISM band with a bandwidth of 1 Mbps. Unlike classic Bluetooth, however, it offers a number of features that make it appealing for low-power wearable applications. It runs at a low data rate, making it a good fit for applications in which devices only exchange state information. The protocol is optimized to burst transmit small amounts of information at regular time intervals, thus allowing the host to stay in very-low-power mode when information is not being sent. It is also optimized to reduce the time required from connection setup to data exchange to just a few milliseconds.
Each layer of the Bluetooth Smart architecture has been optimized to reduce power consumption. It uses a larger physical layer modulation index compared to classic Bluetooth, for example, which helps cut transmit and receive current. The link layer is optimized for quick reconnect, thereby reducing power. The controller implements various key tasks like establishing the connection and ignoring duplicate packets, thus letting the host stay in low-power modes for an extended duration.
With a robust architecture similar to that of classic Bluetooth, Bluetooth Smart supports adaptive frequency hopping with 32-bit CRC. It also supports a special mode known as broadcaster mode, which allows the device to transmit without having to undergo a connection procedure.
The Bluetooth Smart protocol is a perfect fit for wearable devices for the following reasons:
- Protocol isoptimized for ultra-low power.
- Low power consumption design helps minimize battery size, thus reducing the cost, size and weight of the product.
- Compatible with wearable devices exchanging small bursts of information at long intervals.
- Easy to adopt because of the availability of Bluetooth Smart Ready host (dual mode device supporting both classic Bluetooth and Bluetooth Smart) in smartphones. This compares to a proprietary protocol, which would require extra effort to ensure connectivity.
A typical usage profile of a wearable device provides multiple opportunities for the device to go into very-low-power or standby modes (see figure 3).
Figure 3: Normal patterns of use for wearables like activity monitors provide multiple opportunities for the device to go into very-low-power or even standby modes.
Even during the activity period, the wearable device does not necessarily need to send data continuously. The data, whether it be movement detected using a three-axis accelerometer or heart rate monitored via sensor is transmitted periodically, usually once each connection interval. The regular process would be to sense the data, convert it and then send over the Bluetooth Smart connection. For the rest of the time, the system should be put into deep-sleep mode. Note that most silicon solutions available provide multiple power modes that enable trade offs between the current consumption and wake up time for a given power mode. Depending on the time criticality requirements of the system, different modes should be chosen.
We must note that the communication protocol is just one aspect of wearable device design. Apart from the communication interface, wearable devices include multiple other blocks like sensors, an analog front end (AFE) to process the sensor signal, a digital signal processor to filter out environmental noise, storage to log information, a processor to implement multiple system-related functionalities, a battery charger, etc. While designing the system, we need to look at all of the components to get the lowest-power implementation.
Optical heart rate monitoring
Let's consider the example of a wristband that can monitor heart rate (see figure 4). An optical heart rate monitor works on the principle of photoplethysmography (PPG), in which changes in blood volume are processed to yield heart-rate data. In this technique, an LED illuminates the tissue and the reflected signal, which carries the information regarding change in blood volume, is measured using a photodiode. A trans-impedance amplifier (TIA) converts the photocurrent into a voltage that is then converted into a digital signal using an analog-to-digital converter (ADC). This digital signal is then processed in the firmware of the wristband processor to remove DC offset and high-frequency noise, and thus detect heart beats; filtering can also be performed in the analog domain using active filters.
Figure 4: Wristband heart rate monitor analyzes changes to an optical signal caused by variation in blood volume at the sensor. A photodiode reads out the reflected signal and a transimpedance amplifier converts photocurrent to voltage. The analog signal must be digitized and then filtered in order to derive the heart rate data.
Once the device finishes data analysis, it sends the heart rate data to the Bluetooth Smart controller on the wristband and the Bluetooth Smart enabled device using a Bluetooth link. In some optical heart rate monitors, an independent controller in the wearable device is used to do the heart rate processing and it communicates with the main processor via I2C/SPI/IART communication protocol.
In such systems, usage of multiple discrete components not only makes the system complex in terms of different parts being electrically compliant to each other and in testing, but it also increases power consumption (due to lack of control over the AFE when not used), BOM cost, and the size of the PCB.
To address these problems, multiple vendors have released devices based on the system-on-chip (SoC) architecture. These devices not only incorporate a controller but also include analog and digital systems that can be used to implement most of the basic AFE and digital functionalities. One such controller is the Cypress programmable system-on-chip (PSoC) architecture based PSoC 4 BLE. Designed for the wearables market, this SoC includes a 48-MHz ARM®Cortex®M0 CPU, configurable analog and digital resources and an in-built Bluetooth Smart subsystem (see figure 5).
Figure 5: PSoC 4 BLE integrates processor, storage, connectivity, power management, and analog and digital resources in a single package.
In the analog front end, this device has four unconfigured op amps, two low-power comparators, one high-speed SAR ADC and a dedicated capacitive sensing block for user interface applications. On the digital side, it features two serial communication blocks (SCBs) that can be used to implement I2C/UART/SPI protocol, four 16-bit hardware timer counter PWMs (TCPWMs) and four universal digital blocks (UDBs) that can be used to implement digital logic in hardware, just like an FPGA.
To demonstrate the benefits of the SoC approach, let's see how our heart monitor shown in figure 4 changes with the use of the PSoC 4 BLE (see figure 6). In this version, the SoC device implements all functionalities using its internal resources. The only components required outside of the controller are a few passive components and a transistor for driving the LED and as part of the RF-matching network. This integrated approach reduces BOM and PCB size and also gives the designer control over the power consumption of the AFE.
Figure 6: SoC implementation of wristband heart monitor reduces size, BOM and design complexity.
Apart from these advantages, use of SoC architecture also helps reduce the time to market for the following reasons:
- Ready-to-use firmware IP supports system development.
- Because they are part of the same silicon, blocks can operate with each other without incurring much latency. The developer does not have to worry about interfacing them, checking their logic levels, or solving interoperability issues. All these are handled within the device itself.
- Configurable environment provides flexibility to incorporate last minute changes.
In some designs, a Cortex-M0 core may not be sufficient due to the processing power requirements. In such cases, a Cortex-M3 core, like the PSoC 5LP, can be used to handle system-related functions and a Bluetooth Smart based SoC like the PSoC 4 BLE can be used to control the Bluetooth communication along with the AFE and digital logic.
The increasing adoption of Bluetooth Smart Ready devices like smartphones and the distinct low-power advantages of Bluetooth low-energy technology have made Bluetooth Smart the de-facto standard for wearable products. Bluetooth Smart delivers low-power design across all protocol layers, and as a standard protocol, it supports interoperability. By leveraging SoCs targeted at the wearables market, embedded engineers can reduce device size, power consumption, BOM, complexity and design time to get a better product to market faster.
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