Data security concerns? Learn how to stay safe with internal error correcting SRAMs.

Posted on February 13, 2017 by Anuj Chakrapani

Data security is a hot topic among hardware engineers these days, but did you know that the reliability of your system depends on the integrity of the data stored in the system’s memory? In turn, the integrity of the data in the memory depends on the atmospheric conditions around it?

Alpha particles and gamma rays in the surroundings could potentially corrupt the data in your memory device, thereby causing a possibly fatal error in your application. Consider this: at an automobile plant, the arm of an assembly robot is controlled by the configuration data stored in its memory. A corruption of the contents in the memory device could result in improper functioning of the robot, which could result in a standstill in car production.

Thankfully, Cypress has addressed this issue with an error correction code (ECC) algorithm built directly into our SRAM devices. Manufactured on an advanced 65-nm technology node, these SRAM devices use the ECC algorithm to detect and correct single bit errors, offering a 1,000x reduction in bit failure rate. This significantly reduces the overhead of having to run this algorithm in the host device (ASIC or FPGA) driving the SRAM. That robot’s arm will now be spot on every single time!

Check out the video above to see a live demonstration of how a consumer device that emits radiation can cause bit errors in an open-top SRAM without internal ECC. The same radiation has no effect on Cypress’ 65-nm SRAMs with in-built ECC, thereby dramatically improving the reliability of your system and practically eliminating SRAM soft errors.

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